A basic JFET regenerative detector radio receiver:-

found at Radio Frequency Experiment by BH1RBG

The regenerative detector is noted for its great sensitivity.
A regenerative detector uses the principle of positive feedback of a weak input signal,
returned thru an amplifying stage, in order to substantially increase its amplitude .
But, if this feedback is "excessive" the circuit will become a free-running oscillator.
The purpose of the "reaction/regen" control is to set the "operating-point" just less than the self oscillation triggering point.
From observation it is apparent that the "JFET regen detector " section is essentially similar to the well known/reliable "JFET Hartley Oscillator"
However: reaction/regeneration control (point of just breaking into free-running oscillation) is acheived by use of a variable decoupling (AKA 'throttling') capacitor at the JFET drain.

Regenerative Detectors can be Armstrong, Hartley and Colpitts type circuit.

My design is based on an example from Mike WU2D

found at Solid State Boosted Retro Receivers video (22 min mark)

Chuck Kitchin indicates that the operating frequency of a regen detector (when in oscillation) is easily measured:

Inspired by the work of Onno PA2OHH this is my variation of the LED display frequency counter.

The circuitry and operation is very simple, the only trade-off being that
the display must be interpereted from the state of 6 adjacent led's:
the frequency count being the aritmetic "sum" of the illuminated LED's.
This you must do mentally or with pen & paper, but your eye/brain
adapts suprisingly quickly to this presentation.

A 4060 xtal osc/14 stage ripple counter, which gates on/off the 4040 12 stage ripple counter is used to count the incoming signal frequency.
Half of each cycle is used for counting the incoming signal.
On the second half of the cycle, the count is latched in a 74HC574 IC
and the 4040 is also reset to zero.
Mhz position: 15625 Hz sample 64uS period 32uS count, 32uS display
Khz position: 244.1 Hz sample 4.096 mS period 2.048 mS count, 2.048 mS display
The state of the latched count in the 74HC574 is displayed on a row of LED's.
The 6 LED's indicate a frequency value of 8, 4, 2, 1, 0.5, 0.25 (MHz switch pos'n)

and 125, 62, 31, 16, 8, 4 (KHz switch pos'n)
I have used the 74HC 4xxx series (high speed CMOS) family logic IC's
The useable maximum frequency limit (at 5V rail) is 40 MHz.
The LED display upper limit capability is just< 16MHz.
In the MHz switch pos'n the counter displays the most significant 6 highest 'bits' of the count.
Accuracy here would then be 1 part in 64 (about 1.5%)
In the KHz position the counter is over-run (several times)
however provided the input signal is stable we read the truncated frequency count accurate to 4KHz.
Arithmetic addition of the two readings will give a figure of accuracy of 1 bit in 2 power 12 or 1 part in 4096 ( 0.02%)
So you can see; that this very simple idea is indeed quite usefull!

I also recommend that you read Hans Summers excellent follow-up designs and notes,
based on Onno's circuits at Hans Summers G0UPL

See also "VK6FH-freq' counter"