DTMF Decode Store & Display MkII

This circuit is similar to that described previously, except that additional components have been added to display 16 DTMF decodes on a bank of LED type 7-segment displays.


Operation of the circuit is as described before with the following addition: The BCD weighted decode read from IC2/6116 is further converted to 7-segment format by IC4 (74LS48). This feeds a bank of 16, 7-segment common cathode LED type displays; FND503 or similar. Each display has its corresponding "segments" ie. a, b, c etc "bussed" to its neighbours, and each individual cathode connection is current sinked by one of 16 active low outputs of IC7 (74LS154 4 line to 16 line decoder). Because only one cathode is grounded through IC7 at any instant and the segment data changes with each memory address increment, it can be seen that this makes for an efficient display, commonly known as a "multiplexed" type display.

With the switch toggled to "display" an RC oscillator, IC6c (display clock) running at approx 330Hz, clocks IC3 (4040 ripple counter) through 16 sequential memory addresses (00 to 0F) and IC7 also enables on, only one of the 16 LED displays with each incrementation. This produces a 'flicker free' display. With the switch toggled to "write", IC6d then inhibits display clock operation and with IC5d provides a reset pulse to IC3 (ripple counter) which then ensures storage of the next string of DTMF decodes will commence from memory location 0000. The Dv pulse from IC1 will then clock IC3 (ripple counter) with each legitimate decode of a DTMF tone pair.

Note that because of the circuit simplicity: display of only 16 digits is possible with a "roll-around" effect for any decodes following the 16th which are then overwritten into the memory (IC2/6116) starting again at location 0000.