FREQUENCY COUNTER



Will measure and display frequency or period.
Also useable as an event counter.
Upper frequency count limit is about 2 MHz
(or 15MHz in the divide by 10 count position.)
50Hz Mains frequency is used as a reference for all needed frequencies and timings.
We are informed that AC mains frequency is held to close tolerances, therefore the frequency counter should display a similar degree of "accuracy".
Uses 6 off 7 segment displays for readout.
There are many good circuit designs that have a much higher frequency limit,
but this basic design uses only CMOS and TTL family IC's (cheap and readily available).





Frequency counter using LED display


Inspired by the work of Onno PA2OHH this is my build of the LED display frequency counter.
The circuitry and operation is very simple, the only trade-off being that the display must be interpereted from the state of 8 adjacent led's: the frequency count being the aritmetic "sum" of the illuminated LED's.
This you must do mentally or with pen & paper,
but your eye/brain adapts suprisingly quickly to this presentation.



My example was constructed from mostly reclaimed componentry and made to fit in a small metal enclosure. (mustard tin again!)
The need for such a device arose from having to measure (in particular) the VFO frequency of the SDR detector shown elswhere on this site.
A 4020 14 stage ripple counter, which gates on/off the 4040 12 stage ripple counter is used to count the incoming signal frequency.
Half of each cycle is used for counting the incoming signal.
On the second half of the cycle, the count is latched in a 74HC574 IC and the 4040 is reset to zero.
The state of the latched count in the 74HC574 is displayed on a row of LED's.

The 8 LED's indicate a frequency value of 4, 2, 1, 0.5, 0.25, 0.13, 0.06, 0.03 (MHz pos'n) and 125, 62, 31, 16, 8, 4, 2, 1 (KHz pos'n)
Because I have used 'B' 4000 series logic IC's the maximum frequency limit (at 5V rail) is about 4MHz.
I really should have used the 'HC' (high speed CMOS) family variant; for which the upper frequency limit would not be a consideration. (c 50 MHz)
However; once again I have used that which I had readily at hand!
A 74LS74 configured as a divide by 2, D flip-flop; acts as a "prescaler" for both the "clocking" reference (4MHz xtal oscillator) and also the input signal.
The 4MHz quartz oscillator module is used for timing, and 'accuracy' depends on the stability of this unit, which for my purposes is really quite good enough.
Upper freq' limit spec' for the LS family is about 25 MHz.
This then means; an upper freq count limit of about 8 MHz (sufficient to cover the 7~7.5 MHz range of the VFO) can be acheived.
Limited by the capability of the IC's and also the frequency readout.
In the MHz switch pos'n the counter displays the most significant 8 highest 'bits' of the count.
Accuracy here would then be 1 part in 255 (about 0.4%)
In the KHz position the counter is over-run (several times) however provided the input signal is stable we read the truncated frequency count accurate to 1KHz. Arithmetic addition of the two readings will give a figure of accuracy of 1 bit in 2 power 14 or 1 part in 4096 ( 0.02%)
So you can see; that this very simple idea is indeed quite "powerful"
My first reaction when I studied the design was:
"I am really freaked out by this freq' counter" !!
I must set-to and build an example !



Note that the input signal must be at TTL-level .
Since there are a wide variety of possible signal levels from different equipment this counter might find use with; an external VFO buffer amp must then be utilized.



I also recommend that you read Hans Summers excellent follow-up designs and notes (based on Onno's circuit(s) at Hans Summers G0UPL